/*
 * Copyright (C) 2018 Hisilicon Limited.
 *
 * this program is for hisi chip nvme comm
 *
 * This program is free software; you can redistribute it and /or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version
 */

#ifndef _NVME_COMM_DRV_H_
#define _NVME_COMM_DRV_H_

#include <asm/io.h>

#define HISI_MINI 0
#define HISI_CLOUD 1

#define BOARD_MINI_PCIE_CARD 0x0
#define BOARD_MINI_MDC 0x1
#define BOARD_MINI_EVB 0x2
#define BOARD_MINI_OTHERS 0x3
#define BOARD_CLOUD_PCIE_CARD 0x100
#define BOARD_CLOUD_AI_SERVER 0x101
#define BOARD_CLOUD_EVB 0x102
#define BOARD_CLOUD_OTHERS 0x103

#define BOARD_CLOUD_EVB_DEV_NUM 2
#define BOARD_CLOUD_AI_SERVER_DEV_NUM 4

#define NETWORK_PF_0 0
#define NETWORK_PF_1 1

#define PCIE_PF_NUM 2
#define PCIE_PF_0 0
#define PCIE_PF_1 1

// base addr
#define DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE 0x80200
#define DEVDRV_NVME_REG_ALIGN_SIZE 0x1000 /* 4KB */

/* base addr of queue depth */
#define DEVDRV_MSG_CHAN_QUEUE_BASE_ADDR (DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE + 0x24)
/* SQ base address low 32 bits */
#define DEVDRV_MSG_SQ_BASE_ADDR_L (DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE + 0x28)
#define DEVDRV_MSG_SQ_BASE_ADDR_H (DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE + 0x2C)
#define DEVDRV_MSG_CQ_BASE_ADDR_L (DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE + 0x30)
#define DEVDRV_MSG_CQ_BASE_ADDR_H (DEVDRV_NVME_PF_LOCAL_CTRL_REG_BASE + 0x34)

void devdrv_nvme_reg_wr(void __iomem *io_base, u32 offset, u32 val);
void devdrv_nvme_reg_rd(const void __iomem *io_base, u32 offset, u32 *val);

int devdrv_get_chip_type(void);
int devdrv_get_iep_nvme_device_id(void);

void devdrv_set_admin_sq_base(void __iomem *io_base, u64 val);
void devdrv_get_admin_sq_base(const void __iomem *io_base, u64 *val);
void devdrv_raise_int_to_h(void __iomem *io_base, u32 pf, u32 vf, u32 irq);

void devdrv_set_sq_doorbell(void __iomem *io_base, u32 val);
void devdrv_set_cq_doorbell(void __iomem *io_base, u32 val);

void devdrv_get_nvme_irq_sq_db(void __iomem *io_base, u32 irq_num, u32 db_id[], int len, u32 *db_num);
void devdrv_get_nvme_irq_cq_db(void __iomem *io_base, u32 irq_num, u32 db_id[], int len, u32 *db_num);
void devdrv_set_nvme_irq_mask(void __iomem *io_base, u32 irq_num);
void devdrv_set_nvme_irq_unmask(void __iomem *io_base, u32 irq_num);
void devdrv_set_nvme_irq_enbale(void __iomem *io_base, u32 irq_num);


#endif
